Semiconductor devices dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on another structure (e.g., a substrate, another die, etc.) and encased in a plastic protective covering. The die includes functional features, such as for memory cells, processor circuits, and imager devices, as well as interconnects that are electrically connected to the functional features. The interconnects can be electrically connected to terminals outside the protective covering to connect the die to higher level circuitry.
As illustrated in FIG. 1, a semiconductor device 100 (e.g., a three dimensional interconnect (3DI) type of device or a semiconductor package device) can include a die 102 having die interconnects 104 thereon connected to a substrate structure 106 (e.g., a printed circuit board (PCB), a semiconductor or wafer-level substrate, another die, etc.) having substrate interconnects 108 thereon. The die 102 and the substrate structure 106 can be electrically coupled to each other through the die interconnects 104 and the substrate interconnects 108. Further, the die interconnects 104 and the substrate interconnects 108 can be directly contacted each other (e.g., through a bonding process, such as diffusion bonding or hybrid bonding) or through an intermediate structure (e.g., solder). The semiconductor device 100 can further include an encapsulant, such as an underfill 110, surrounding or encapsulating the die 102, the die interconnects 104, the substrate structure 106, the substrate interconnects 108, a portion thereof, or a combination thereof.
With technological advancements in other areas and increasing applications, the market is continuously looking for faster and smaller devices. To meet the market demand, physical sizes or dimensions of the semiconductor devices are being pushed to the limit. For example, efforts are being made to reduce a separation distance between the die 102 and the substrate structure 106 (e.g., for 3DI devices and die-stacked packages).
However, due to various factors (e.g., viscosity level of the underfill 110, trapped air/gases, uneven flow of the underfill 110, space between the interconnects, etc.), the encapsulation process can be unreliable, such as leaving voids 114 between the die 102 and the substrate structure 106 (e.g., with portions of the interconnects failing to directly contact the underfill 110). The voids 114 can cause shorting and leakage between the interconnects (e.g., between the substrate interconnect 108 and/or between the die interconnects 104), causing an electrical failure for the semiconductor device 100. Further, as the device grows smaller, the manufacturing cost can grow (e.g., based on using nano-particle underfill instead of traditional underfill).